Over the last several years, DSPs have become an important tool, particularly in the real-time modification of signal streams. They have found use in all manner of electronic devices and will continue to grow in power and popularity.
Those skilled in the art are familiar with DSP architecture in general. Conventional DSPs employ a pipeline through which pass data representing a signal to be processed. An execution core performs various mathematical and logical operations on the data to effect changes therein. Memory is coupled to the execution core. The memory contains not only instructions concerning the way in which the data are to be modified, but also further data that may be employed in conjunction with executing the instructions.
It becomes important at this point to discuss two details with respect to the way in which DSP memory may be architected. First, two fundamental DSP architectures exist that are distinguished from one another by how they interact with memory. So-called “von Neumann” architecture DSPs unify instructions and data in a single memory and a single bus. So-called “Harvard” architecture DSPs split instructions and data between two separate memories and buses. The tradeoff is simplicity (von Neumann) versus speed (Harvard).
Second, more sophisticated DSPs stratify memory in an effort to balance speed, cost and power consumption. In a perfect and simple world, a DSP's memory would be extremely fast, low power, arbitrarily large and on the same physical substrate. Unfortunately, very fast memory is very expensive and requires lots of power and arbitrarily large memory takes an arbitrarily large amount of room on a given substrate. Tempering those requirements with today's commercial concerns regarding both chip and system cost, flexibility and power consumption, modern DSP architecture calls for memory to be stratified, perhaps into three or more layers.
Assuming for the moment that three layers are desired, those might be (1) an extremely small, fast cache, located on the same physical substrate as the processing core of the DSP, that contains very little, but highly relevant instructions or data, (2) a somewhat larger, somewhat slower memory, still located on the same physical substrate as the processing core of the DSP, that contains relevant instructions or data and (3) an external memory that is as large as need be to contain the entirety of a program and data that the DSP is to use, but that is located on a separate physical substrate and accessible only through a comparatively slow external memory interface. While keeping the external memory on a separate substrate increases flexibility in system design and allows the DSP's chip size to remain small, external memory requires its own power. Therefore, every external memory access comes at the cost of some power consumption that should be minimized in power-consumption-sensitive (typically battery-powered) systems. It should also be noted that processors of all types, including ubiquitous microprocessors, employ the same stratification strategy to balance their speed and cost goals.
Given this memory stratification, designers have set about for years to increase performance by developing a number of schemes to avoid latencies and power consumption associated with gaining access to more distant echelons of memory for purposes of loading instructions or loading and storing data. Intelligent guesses concerning instructions and data that may be useful in the near future can be employed to great advantage to retrieve ahead of time (or “prefetch”) such instructions or data into faster memory. However, further improvement remains possible.
Accordingly, what is needed in the art is a better way to manage stratified memory to increase processor performance. More specifically, what is needed is a mechanism that prefetches instructions into a processor more effectively, such that processor performance (speed and power consumption) is improved. Most specifically, a mechanism to improve overall DSP performance is a primary objective.